Stress imposed on the channel of transistors is used to enhance transistor performance. For example, stress memorization techniques are used to impose tensile stress on the NMOS transistor channel to enhance NMOS transistor performance and silicon-germanium replacement source and drains are used to impose compressive stress on the PMOS transistor channel to enhance PMOS transistor performance.
Variation in stress imposed on the transistor channel transistor-to-transistor causes variation in the drive current (Ids) transistor-to-transistor. One source of variation in stress is active overlap of the transistor gate. Variation in the active overlap of the transistor gate transistor-to-transistor results in variation in the drive current transistor-to-transistor. Typically designers loosen their transistor design margins so that the integrated circuit can operate properly in spite of the stress induces transistor-to-transistor mismatch in the drive current. Loosening transistor design margins may result in a reduction in performance of the integrated circuit.